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SubjectRe: [PATCH 2/2] x86/resctrl: Support CPUID enumeration of MBM counter width
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Hi Fenghua,

On 4/2/2020 5:05 PM, Fenghua Yu wrote:
> On Wed, Apr 01, 2020 at 10:51:02AM -0700, Reinette Chatre wrote:
>> The original Memory Bandwidth Monitoring (MBM) architectural
>> definition defines counters of up to 62 bits in the
>> IA32_QM_CTR MSR while the first-generation MBM implementation
>> uses statically defined 24 bit counters.
>>
>> @@ -856,6 +856,8 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
>>
>> static void init_cqm(struct cpuinfo_x86 *c)
>> {
>> + c->x86_cache_mbm_width_offset = -1;
>> +
>> if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
>> c->x86_cache_max_rmid = -1;
>> c->x86_cache_occ_scale = -1;
>> @@ -875,6 +877,9 @@ static void init_cqm(struct cpuinfo_x86 *c)
>>
>> c->x86_cache_max_rmid = ecx;
>> c->x86_cache_occ_scale = ebx;
>> + /* EAX contents is only defined for Intel CPUs */
>> + if (c->x86_vendor == X86_VENDOR_INTEL)
>> + c->x86_cache_mbm_width_offset = eax & 0xff;
>
> Is it reliable to read eax which is reserved on older platforms that
> don't support the feature?

The new ISE specification contains an architectural redefinition of EAX.

>
> Seems the code assumes the reserved eax is 0 on those platforms. Is it
> reliable?

Testing on BDW, SKX, and CLX confirmed that EAX is 0. This addition thus
results in no functional change on these systems with them continuing to
use the original MBM width of 24.

Reinette

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