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SubjectRe: [PATCH v1 5/8] vfio/type1: Report 1st-level/stage-1 format to userspace
On Wed, Apr 01, 2020 at 03:01:12PM +0200, Auger Eric wrote:
> >>> header = vfio_info_cap_add(caps, sizeof(*nesting_cap),
> >>> @@ -2254,6 +2309,7 @@ static int vfio_iommu_info_add_nesting_cap(struct
> >> vfio_iommu *iommu,
> >>> /* nesting iommu type supports PASID requests (alloc/free) */
> >>> nesting_cap->nesting_capabilities |= VFIO_IOMMU_PASID_REQS;
> >> What is the meaning for ARM?
> >
> > I think it's just a software capability exposed to userspace, on
> > userspace side, it has a choice to use it or not. :-) The reason
> > define it and report it in cap nesting is that I'd like to make
> > the pasid alloc/free be available just for IOMMU with type
> > VFIO_IOMMU_TYPE1_NESTING. Please feel free tell me if it is not
> > good for ARM. We can find a proper way to report the availability.
> Well it is more a question for jean-Philippe. Do we have a system wide
> PASID allocation on ARM?

We don't, the PASID spaces are per-VM on Arm, so this function should
consult the IOMMU driver before setting flags. As you said on patch 3,
nested doesn't necessarily imply PASID support. The SMMUv2 does not
support PASID but does support nesting stages 1 and 2 for the IOVA space.
SMMUv3 support of PASID depends on HW capabilities. So I think this needs
to be finer grained:

Does the container support:
-> Yes for VT-d 3
-> No for Arm SMMU
-> Yes for VT-d 3
-> Sometimes for SMMUv2
-> No for SMMUv3 (if we go with BIND_PASID_TABLE, which is simpler due to
PASID tables being in GPA space.)
-> No for VT-d
-> Sometimes for SMMUv3

Any bind support implies VFIO_IOMMU_CACHE_INVALIDATE support.

> >>> + nesting_cap->stage1_formats = formats;
> >> as spotted by Kevin, since a single format is supported, rename
> >
> > ok, I was believing it may be possible on ARM or so. :-) will
> > rename it.

Yes I don't think an u32 is going to cut it for Arm :( We need to describe
all sorts of capabilities for page and PASID tables (granules, GPA size,
ASID/PASID size, HW access/dirty, etc etc.) Just saying "Arm stage-1
format" wouldn't mean much. I guess we could have a secondary vendor
capability for these?


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