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SubjectRE: [PATCH V2 04/10] clk: imx8mp: Define gates for pll1/2 fixed dividers
Date
> From: Peng Fan <peng.fan@nxp.com>
> Sent: Thursday, March 12, 2020 6:20 PM
>
> Inspried from
> commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
>
> On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each
> with their own gate. Only one of these gates (the one "dividing" by
> one) is currently defined and it's incorrectly set as the parent of all the
> fixed-factor dividers.
>
> Add the other 8 gates to the clock tree between sys_pll1/2_bypass and the fixed
> dividers.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

Regards
Aisheng
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