Messages in this thread |  | | Subject | Re: [PATCH] iommu/vt-d: Fix PASID cache flush | From | Auger Eric <> | Date | Tue, 31 Mar 2020 11:28:17 +0200 |
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Hi Jacob,
On 3/31/20 1:25 AM, Jacob Pan wrote: > PASID cache type and shift of granularity bits are missing in > the current code. > > Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table > interface") > > Cc: Eric Auger <eric.auger@redhat.com> > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com>
Thanks
Eric
> --- > drivers/iommu/intel-pasid.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c > index 22b30f10b396..57d05b0fbafc 100644 > --- a/drivers/iommu/intel-pasid.c > +++ b/drivers/iommu/intel-pasid.c > @@ -365,7 +365,8 @@ pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, > { > struct qi_desc desc; > > - desc.qw0 = QI_PC_DID(did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid); > + desc.qw0 = QI_PC_DID(did) | QI_PC_GRAN(QI_PC_PASID_SEL) | > + QI_PC_PASID(pasid) | QI_PC_TYPE; > desc.qw1 = 0; > desc.qw2 = 0; > desc.qw3 = 0; >
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