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SubjectRe: [PATCH V10 09/11] iommu/vt-d: Cache virtual command capability register
On Sat, 28 Mar 2020 10:04:38 +0000
"Tian, Kevin" <kevin.tian@intel.com> wrote:

> > From: Jacob Pan <jacob.jun.pan@linux.intel.com>
> > Sent: Saturday, March 21, 2020 7:28 AM
> >
> > Virtual command registers are used in the guest only, to prevent
> > vmexit cost, we cache the capability and store it during
> > initialization.
> >
> > Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> > Reviewed-by: Eric Auger <eric.auger@redhat.com>
> > Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
> >
> > ---
> > v7 Reviewed by Eric & Baolu
> > ---
> > ---
> > drivers/iommu/dmar.c | 1 +
> > include/linux/intel-iommu.h | 5 +++++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
> > index 4d6b7b5b37ee..3b36491c8bbb 100644
> > --- a/drivers/iommu/dmar.c
> > +++ b/drivers/iommu/dmar.c
> > @@ -963,6 +963,7 @@ static int map_iommu(struct intel_iommu *iommu,
> > u64 phys_addr)
> > warn_invalid_dmar(phys_addr, " returns all ones");
> > goto unmap;
> > }
> > + iommu->vccap = dmar_readq(iommu->reg + DMAR_VCCAP_REG);
> >
> > /* the registers might be more than one page */
> > map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap),
> > diff --git a/include/linux/intel-iommu.h
> > b/include/linux/intel-iommu.h index 43539713b3b3..ccbf164fb711
> > 100644 --- a/include/linux/intel-iommu.h
> > +++ b/include/linux/intel-iommu.h
> > @@ -194,6 +194,9 @@
> > #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
> > #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping
> > Control */
> >
> > +/* Virtual command interface capabilities */
>
> capabilities -> capability
Will do, I was thinking the future :)

Thanks,

Jacob
>
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
>
> > +#define vccap_pasid(v) ((v & DMA_VCS_PAS)) /* PASID
> > allocation */
> > +
> > /* IOTLB_REG */
> > #define DMA_TLB_FLUSH_GRANU_OFFSET 60
> > #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
> > @@ -287,6 +290,7 @@
> >
> > /* PRS_REG */
> > #define DMA_PRS_PPR ((u32)1)
> > +#define DMA_VCS_PAS ((u64)1)
> >
> > #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts)
> > \
> > do
> > {
> > \ @@ -537,6 +541,7 @@ struct intel_iommu { u64
> > reg_size; /* size of hw register set */ u64 cap;
> > u64 ecap;
> > + u64 vccap;
> > u32 gcmd; /* Holds TE, EAFL. Don't need
> > SRTP, SFL, WBF */
> > raw_spinlock_t register_lock; /* protect register
> > handling */ int seq_id; /* sequence id of the
> > iommu */ --
> > 2.7.4
>

[Jacob Pan]

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