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SubjectRe: [PATCH v9 04/11] pwm: clps711x: Use 64-bit division macro
On Tue, Mar 17, 2020 at 11:22:06PM +0100, Arnd Bergmann wrote:
> > diff --git a/drivers/pwm/pwm-clps711x.c b/drivers/pwm/pwm-clps711x.c
> > index 924d39a..ba9500a 100644
> > --- a/drivers/pwm/pwm-clps711x.c
> > +++ b/drivers/pwm/pwm-clps711x.c
> > @@ -43,7 +43,7 @@ static void clps711x_pwm_update_val(struct clps711x_chip *priv, u32 n, u32 v)
> > static unsigned int clps711x_get_duty(struct pwm_device *pwm, unsigned int v)
> > {
> > /* Duty cycle 0..15 max */
> > - return DIV_ROUND_CLOSEST(v * 0xf, pwm->args.period);
> > + return DIV64_U64_ROUND_CLOSEST(v * 0xf, pwm->args.period);
> > }
>
> Is it actually going to exceed U32_MAX? If not, a type cast may be
> more appropriate here than the expensive 64-bit division.

With the final change in this patch series, the framework will support
periods that exceed U32_MAX. My concern is that using a typecast would
mean that in those cases, this driver will not support > U32_MAX values.
Using DIV64_U64_ROUND_CLOSEST makes the driver future proof and able to
handle > U32_MAX values correctly. What do you think?

Thank you.

Guru Das.

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