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SubjectRe: [PATCH v2] MIPS: c-r4k: Invalidate BMIPS5000 ZSCM prefetch lines
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This is needed on dma reads from device.  

Kamal


> On Mar 11, 2020, at 5:44 PM, Thomas Bogendoerfer <tsbogend@alpha.franken.de> wrote:
>
> On Wed, Mar 11, 2020 at 01:54:23PM -0700, Florian Fainelli wrote:
>>> On 2/7/20 2:33 PM, Kamal Dasu wrote:
>>> Zephyr secondary cache is 256KB, 128B lines. 32B sectors. A secondary cache
>>> line can contain two instruction cache lines (64B), or four data cache
>>> lines (32B). Hardware prefetch Cache detects stream access, and prefetches
>>> ahead of processor access. Add support to invalidate BMIPS5000 cpu zephyr
>>> secondary cache module (ZSCM) on DMA from device so that data returned is
>>> coherent during DMA read operations.
>>>
>>> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>>
>> Thomas can review and apply this patch? Thank you!
>
> looks good to me. I only wonder whether r4k_dma_cache_wbinv() also
> needs this ?
>
> Thomas.
>
> --
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea. [ RFC1925, 2.3 ]
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