Messages in this thread |  | | Date | Tue, 4 Feb 2020 19:32:30 +0000 | From | Russell King - ARM Linux admin <> | Subject | Re: [RFC net-next 6/8] net: phylink: Configure MAC/PCS when link is up without PHY |
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On Tue, Feb 04, 2020 at 06:43:18PM +0100, Andrew Lunn wrote: > > There, there is one MAC, but there are multiple different PCS - one > > for SGMII and 1000base-X, another for 10G, another for 25G, etc. > > These PCS are accessed via a MDIO adapter embedded in each of the > > MAC hardware blocks. > > Hi Russell > > Marvell mv88e6390X switches are like this is a well. There is a PCS > for SGMII and 1000Base-X, and a second one for 10G. And it dynamically > swaps between them depending on the port mode, the so called cmode. > > So a generic solution is required, and please take your time to build > one.
Well, DSA is quite a mixed bag...
As far as I can work out, the situation with the CPU and DSA ports is quite hopeless - you've claimed that a change in phylink has broken it, I can't find what that may be. The fact is, phylink has never had any link information for DSA links when no fixed-link property has been specified in DT. As I've already said in a previous email about this, I can't see *any* sane way to fix that - but there was no response.
On a more positive note...
The mac_link_up() changes that I've talked about should work for DSA, if only there was a reasonable way to reconfigure the ports. If you look at the "phy" branch, you will notice that there's a patch there - "net: mv88e6xxx: use resolved link config in mac_link_up()" which adds the support to configure the MAC manually. It's rather messy, and I see no way to deal with the pause settings. There is support in some Marvell DSA switches to force flow control but that's not supported through the current mid-layer at all (port_set_pause doesn't do it.) I'm not sure whether the "mv88e6xxx_phy_is_internal()" check there is the right test for every DSA switch correct either.
What is missing is reading the results from the PCS (aka serdes) and forwarding them into phylink - I did have a quick look at how that might be possible, but the DSA code structure (consisting of multiple mid-layers) makes it hard without rewriting quite a lot of code. That's fine if you know all the DSA chips inside out, but I don't - and that's where we need someone who has the knowledge of all DSA switches that we support. Or, we get rid of the multiple mid-layers and switch to a library approach, so that we can modify support for one DSA switch without affecting everything. It may be a simple matter of dropping the existing serdes workaround, but I'm not sure at the moment.
I've tried this code out on the ZII rev B, I haven't tried it on the rev C which has the 6390 switches yet.
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