Messages in this thread |  | | From | Harini Katakam <> | Subject | [PATCH v2 0/2] TSO bug fixes | Date | Mon, 3 Feb 2020 18:48:00 +0530 |
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An IP errata was recently discovered when testing TSO enabled versions with perf test tools where a false amba error is reported by the IP. Some ways to reproduce would be to use iperf or applications with payload descriptor sizes very close to 16K. Once the error is observed TXERR (or bit 6 of ISR) will be constantly triggered leading to a series of tx path error handling and clean up. Workaround the same by limiting this size to 0x3FC0 as recommended by Cadence. There was no performance impact on 1G system that I tested with.
Note on patch 1: The alignment code may be unused but leaving it there in case anyone is using UFO.
Added Fixes tag to patch 1.
Harini Katakam (2): net: macb: Remove unnecessary alignment check for TSO net: macb: Limit maximum GEM TX length in TSO
drivers/net/ethernet/cadence/macb_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
-- 2.7.4
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