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SubjectRe: [PATCH v3 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:

> These two things were in one function. Split into two. This looks
> like it's duplicating some code, but don't worry. This is is just in
> preparation for future changes.
>
> This is intended to have zero functional change and will just make
> future patches easier to understand.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Rob Clark <robdclark@gmail.com>
> Reviewed-by: Rob Clark <robdclark@gmail.com>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 33 +++++++++++++++++++--------
> 1 file changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 43abf01ebd4c..2fb9370a76e6 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -417,6 +417,24 @@ static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
> REFCLK_FREQ(i));
> }
>
> +static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
> +{
> + unsigned int bit_rate_mhz, clk_freq_mhz;
> + unsigned int val;
> + struct drm_display_mode *mode =
> + &pdata->bridge.encoder->crtc->state->adjusted_mode;
> +
> + /* set DSIA clk frequency */
> + bit_rate_mhz = (mode->clock / 1000) *
> + mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
> + clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
> +
> + /* for each increment in val, frequency increases by 5MHz */
> + val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
> + (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
> + regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
> +}
> +
> /**
> * LUT index corresponds to register value and
> * LUT values corresponds to dp data rate supported
> @@ -426,22 +444,16 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
> 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
> };
>
> -static void ti_sn_bridge_set_dsi_dp_rate(struct ti_sn_bridge *pdata)
> +static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata)
> {
> - unsigned int bit_rate_mhz, clk_freq_mhz, dp_rate_mhz;
> - unsigned int val, i;
> + unsigned int bit_rate_mhz, dp_rate_mhz;
> + unsigned int i;
> struct drm_display_mode *mode =
> &pdata->bridge.encoder->crtc->state->adjusted_mode;
>
> /* set DSIA clk frequency */
> bit_rate_mhz = (mode->clock / 1000) *
> mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
> - clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
> -
> - /* for each increment in val, frequency increases by 5MHz */
> - val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
> - (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
> - regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
>
> /* set DP data rate */
> dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
> @@ -510,7 +522,8 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> val);
>
> /* set dsi/dp clk frequency value */
> - ti_sn_bridge_set_dsi_dp_rate(pdata);
> + ti_sn_bridge_set_dsi_rate(pdata);
> + ti_sn_bridge_set_dp_rate(pdata);
>
> /* enable DP PLL */
> regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
> --
> 2.24.1.735.g03f4e72817-goog
>

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