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Subject[PATCH 4.14 024/237] perf/x86/amd: Add missing L2 misses event spec to AMD Family 17hs event map
From: Kim Phillips <>

commit 25d387287cf0330abf2aad761ce6eee67326a355 upstream.

Commit 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h"),
claimed L2 misses were unsupported, due to them not being found in its
referenced documentation, whose link has now moved [1].

That old documentation listed PMCx064 unit mask bit 3 as:

"LsRdBlkC: LS Read Block C S L X Change to X Miss."

and bit 0 as:

"IcFillMiss: IC Fill Miss"

We now have new public documentation [2] with improved descriptions, that
clearly indicate what events those unit mask bits represent:

Bit 3 now clearly states:

"LsRdBlkC: Data Cache Req Miss in L2 (all types)"

and bit 0 is:

"IcFillMiss: Instruction Cache Req Miss in L2."

So we can now add support for L2 misses in perf's genericised events as
PMCx064 with both the above unit masks.

[1] The commit's original documentation reference, "Processor Programming
Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors",
originally available here:

is now available here:

[2] "Processor Programming Reference (PPR) for Family 17h Model 31h,
Revision B0 Processors", available here:

Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h")
Reported-by: Babu Moger <>
Signed-off-by: Kim Phillips <>
Signed-off-by: Peter Zijlstra (Intel) <>
Signed-off-by: Ingo Molnar <>
Tested-by: Babu Moger <>
Signed-off-by: Greg Kroah-Hartman <>

arch/x86/events/amd/core.c | 1 +
1 file changed, 1 insertion(+)

--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -245,6 +245,7 @@ static const u64 amd_f17h_perfmon_event_

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