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SubjectRe: [PATCH v2 3/3] perf vendor events amd: update Zen1 events to V2
> OSRR for AMD Family 17h processors, Models 00h-2Fh, 56255 Rev 3.03 - July, 2018
I have included this for v3 that I will submit later, including all the
changes for the FPU counters. Sorry, I messed up copy-pasting the text
and forgot to change the trailing pipe number.
> and their counts don't seem to match up very well when running
> various workloads. The microarchitecture is likely to have changed
> in this area from families prior to 17h, so a MAB alloc can likely
> count different events than what is presumed here: a Data cache
> load/store/prefetch miss.
>
> I think it's safer to just leave the PPR text "LS MAB Allocates
> by Type" as-is, instead of assuming they are L1 load/store misses.
> What do you think?

I did some checking accross PPRs, and this counter seems to have changed
names multiple times throughout the PPR revisions.

Zen1 PPR (54945 Rev 1.14 - April 15, 2017) lists counter called "LsMabAllocPipe"
with 5 subcounters that have different names compared to ones we see in
the mainline right now. PPRs for stepping B2
onwards change this to the 3 sub-counter and primary counter name
we see right now. This public description still changes accross various
PPR revisions, which is why I had this set to what it was. The lastest
PPR I can find is indeed lists it as "LS MAB Allocates by Type";
I will change it to that with the fuffix of tehe sub-counter name. Since
the same counter is in Zen2 as well, I will make the same changes there
too.

Let me know if this sounds good to you!
Best,
Vijay

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