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SubjectRe: [PATCH AUTOSEL 5.5 218/542] ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879
On Fri, Feb 14, 2020 at 12:34:19PM -0600, Suman Anna wrote:
>Hi Sasha,
>On 2/14/20 9:43 AM, Sasha Levin wrote:
>> From: Suman Anna <>
>> [ Upstream commit 2f14101a1d760db72393910d481fbf7768c44530 ]
>> Errata Title:
>> i879: DSP MStandby requires CD_EMU in SW_WKUP
>> Description:
>> The DSP requires the internal emulation clock to be actively toggling
>> in order to successfully enter a low power mode via execution of the
>> IDLE instruction and PRCM MStandby/Idle handshake. This assumes that
>> other prerequisites and software sequence are followed.
>> Workaround:
>> The emulation clock to the DSP is free-running anytime CCS is connected
>> via JTAG debugger to the DSP subsystem or when the CD_EMU clock domain
>> is set in SW_WKUP mode. The CD_EMU domain can be set in SW_WKUP mode
>> via the CM_EMU_CLKSTCTRL [1:0]CLKTRCTRL field.
>> Implementation:
>> This patch implements this workaround by denying the HW_AUTO mode
>> for the EMU clockdomain during the power-up of any DSP processor
>> and re-enabling the HW_AUTO mode during the shutdown of the last
>> DSP processor (actually done during the enabling and disabling of
>> the respective DSP MDMA MMUs). Reference counting has to be used to
>> manage the independent sequencing between the multiple DSP processors.
>> This switching is done at runtime rather than a static clockdomain
>> flags value to meet the target power domain state for the EMU power
>> domain during suspend.
>> Note that the DSP MStandby behavior is not consistent across all
>> boards prior to this fix. Please see commit 45f871eec6c0 ("ARM:
>> OMAP2+: Extend DRA7 IPU1 MMU pdata quirks to DSP MDMA MMUs") for
>> details.
>> Signed-off-by: Suman Anna <>
>> Signed-off-by: Tony Lindgren <>
>> Signed-off-by: Sasha Levin <>
>You can drop this from the 5.5-stable queue. Mainline doesn't yet boot
>the processors, so this is not needed for stable queue.

Now dropped, thank you.


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