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SubjectRe: [PATCH] MIPS: cavium_octeon: Fix syncw generation.

Mark Tomlinson wrote:
> The Cavium Octeon CPU uses a special sync instruction for implementing
> wmb, and due to a CPU bug, the instruction must appear twice. A macro
> had been defined to hide this:
> #define __SYNC_rpt(type) (1 + (type == __SYNC_wmb))
> which was intended to evaluate to 2 for __SYNC_wmb, and 1 for any other
> type of sync. However, this expression is evaluated by the assembler,
> and not the compiler, and the result of '==' in the assembler is 0 or
> -1, not 0 or 1 as it is in C. The net result was wmb() producing no code
> at all. The simple fix in this patch is to change the '+' to '-'.

Applied to mips-fixes.

> commit 97e914b7de3c
> Fixes: bf92927251b3 ("MIPS: barrier: Add __SYNC() infrastructure")
> Signed-off-by: Mark Tomlinson <>
> Tested-by: Chris Packham <>
> Signed-off-by: Paul Burton <>


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