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SubjectRe: [PATCH 0/7] microblaze: Define SMP safe operations
On Wed, Feb 12, 2020 at 04:42:22PM +0100, Michal Simek wrote:

> Microblaze has 32bit exclusive load/store instructions which should be used
> instead of irq enable/disable. For more information take a look at
> https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug984-vivado-microblaze-ref.pdf
> starting from page 25.

> arch/microblaze/include/asm/Kbuild | 1 -
> arch/microblaze/include/asm/atomic.h | 265 ++++++++++++++++++-
> arch/microblaze/include/asm/bitops.h | 189 +++++++++++++
> arch/microblaze/include/asm/cmpxchg.h | 87 ++++++
> arch/microblaze/include/asm/cpuinfo.h | 2 +-
> arch/microblaze/include/asm/pgtable.h | 19 +-
> arch/microblaze/include/asm/spinlock.h | 240 +++++++++++++++++
> arch/microblaze/include/asm/spinlock_types.h | 25 ++
> arch/microblaze/kernel/cpu/cache.c | 154 ++++++-----
> arch/microblaze/kernel/cpu/cpuinfo.c | 38 ++-
> arch/microblaze/kernel/cpu/mb.c | 207 ++++++++-------
> arch/microblaze/kernel/timer.c | 2 +-
> arch/microblaze/mm/consistent.c | 8 +-
> 13 files changed, 1040 insertions(+), 197 deletions(-)
> create mode 100644 arch/microblaze/include/asm/bitops.h
> create mode 100644 arch/microblaze/include/asm/spinlock.h
> create mode 100644 arch/microblaze/include/asm/spinlock_types.h

I'm missing asm/barrier.h

Also that PDF (thanks for that!), seems light on memory ordering
details.

Your comment:

+/*
+ * clear_bit doesn't imply a memory barrier
+ */

worries me, because that would imply your ll/sc does not impose order,
but then you also don't have any explicit barriers in your locking
primitives or atomics where required.

In the PDF I only find MBAR; is that what smp_mb() ends up being?

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