Messages in this thread |  | | Date | Tue, 29 Dec 2020 22:31:46 +0100 | From | Thomas Petazzoni <> | Subject | Re: [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect. |
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On Mon, 28 Dec 2020 15:05:10 +0100 Nadeem Athani <nadeem@cadence.com> wrote:
> +static void cdns_pcie_retrain(struct cdns_pcie *pcie)
Shouldn't this propagate a return value ?
> +{ > + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; > + u16 lnk_stat, lnk_ctl; > + > + /* > + * Set retrain bit if current speed is 2.5 GB/s, > + * but the PCIe root port support is > 2.5 GB/s. > + */ > + > + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + > + PCI_EXP_LNKCAP)); > + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) > + return; > + > + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); > + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { > + lnk_ctl = cdns_pcie_rp_readw(pcie, > + pcie_cap_off + PCI_EXP_LNKCTL); > + lnk_ctl |= PCI_EXP_LNKCTL_RL; > + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, > + lnk_ctl); > + > + if (cdns_pcie_host_wait_for_link(pcie)) > + return;
Here, shouldn't you return the status of cdns_pcie_host_wait_for_link(), to propagate whether the PCIe link indeed came up after the retrain ?
Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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