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SubjectRe: [PATCH v13 07/15] iommu/smmuv3: Allow stage 1 invalidation with unmanaged ASIDs
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Thanks for your reply. We are testing vSVA, and will let you know if
other problems are found.

On 2020/12/1 21:58, Auger Eric wrote:
> Hi Xingang,
>
> On 12/1/20 2:33 PM, Xingang Wang wrote:
>> Hi Eric
>>
>> On Wed, 18 Nov 2020 12:21:43, Eric Auger wrote:
>>> @@ -1710,7 +1710,11 @@ static void arm_smmu_tlb_inv_context(void *cookie)
>>> * insertion to guarantee those are observed before the TLBI. Do be
>>> * careful, 007.
>>> */
>>> - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
>>> + if (ext_asid >= 0) { /* guest stage 1 invalidation */
>>> + cmd.opcode = CMDQ_OP_TLBI_NH_ASID;
>>> + cmd.tlbi.asid = ext_asid;
>>> + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid;
>>> + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
>>
>> Found a problem here, the cmd for guest stage 1 invalidation is built,
>> but it is not delivered to smmu.
>>
>
> Thank you for the report. I will fix that soon. With that fixed, have
> you been able to run vSVA on top of the series. Do you need other stuff
> to be fixed at SMMU level? As I am going to respin soon, please let me
> know what is the best branch to rebase to alleviate your integration.
>
> Best Regards
>
> Eric
>
> .
>

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