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Subject[PATCH v6 0/6] mmc: sdhci-of-aspeed: Expose phase delay tuning
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Hello,

This series implements support for the MMC core clk-phase-* devicetree bindings
in the Aspeed SD/eMMC driver. The relevant register was exposed on the AST2600
and is present for both the SD/MMC controller and the dedicated eMMC
controller.

v6 simply removes the typedef from v5 in favour of a struct containing the
phase array.

I've just done a quick build test of v6 given the small change and more
extensive testing done with v5.

v5 can be found here:

https://lore.kernel.org/linux-mmc/20201208012615.2717412-1-andrew@aj.id.au/

Please review!

Cheers,

Andrew

Andrew Jeffery (6):
mmc: core: Add helper for parsing clock phase properties
mmc: sdhci-of-aspeed: Expose clock phase controls
mmc: sdhci-of-aspeed: Add AST2600 bus clock support
mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations
MAINTAINERS: Add entry for the ASPEED SD/MMC driver
ARM: dts: rainier: Add eMMC clock phase compensation

MAINTAINERS | 9 +
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 1 +
drivers/mmc/core/host.c | 44 ++++
drivers/mmc/host/Kconfig | 14 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-aspeed-test.c | 100 ++++++++
drivers/mmc/host/sdhci-of-aspeed.c | 251 ++++++++++++++++++-
include/linux/mmc/host.h | 13 +
8 files changed, 422 insertions(+), 11 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-of-aspeed-test.c

--
2.27.0

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