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SubjectRe: [PATCH 6/9] ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controller
On Mon 02 Nov 20, 14:44, Maxime Ripard wrote:
> On Mon, Nov 02, 2020 at 11:25:22AM +0100, Paul Kocialkowski wrote:
> > Hi,
> >
> > On Mon 02 Nov 20, 11:12, Maxime Ripard wrote:
> > > On Sat, Oct 31, 2020 at 07:21:34PM +0100, Paul Kocialkowski wrote:
> > > > The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209.
> > > > Its address follows the sytsem controller block, which was previously
> > > > incorrectly described as spanning over 0x1000 address bytes.
> > >
> > > Is it after, or right in the middle of it?
> >
> > That's up for interpretation actually:
> > - The V3 datasheet mentions that System Control is 0x01C00000 --- 0x01C00FFF;
> > - In practice, sunxi_sram.c uses a regmap with max_reg set to 0x30 for the
> > V3s/H3 so this gives us some room.
> >
> > Looking at other SoCs with the same setup (take sun8i-r40 for instance),
> > system-control is limited to 0x30 and the NMI controller follows it.
> > In the case of R40, the SRAM controlled is also said to be 4K-long in the
> > Allwinner docs.
> >
> > So all in all, this leads me to believe that the system-controller instance
> > stops well before 0x1c000d0 on the V3s as well. Otherwise, we should also
> > make the R40 consistent.
>
> That's a bit unfortunate, but yeah, I guess we want to remain consistent here.

Honestly I think the Allwinner docs are plain wrong on this one.
IIRC they used to describe the NMI as a separate controller in the memory
map. I think they just overlook it now and copy/paste 4K size for each
controller regardless of the actual hardware, so I'm not very worried.

Cheers,

Pauls

--
Developer of free digital technology and hardware support.

Website: https://www.paulk.fr/
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