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Subject[PATCH 9/9] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
Date
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 39 +++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index c4751fe9edfd..94fd9ce4223e 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -267,6 +267,8 @@ struct cdns_sierra_phy {
struct clk *clk;
struct clk *cmn_refclk_dig_div;
struct clk *cmn_refclk1_dig_div;
+ struct clk *pll_cmnlc;
+ struct clk *pll_cmnlc1;
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -847,6 +849,41 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
}
sp->cmn_refclk1_dig_div = clk;

+ clk = devm_clk_get_optional(dev, "pll_cmnlc");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc = clk;
+
+ clk = devm_clk_get_optional(dev, "pll_cmnlc1");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc1 clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc1 = clk;
+
+ return 0;
+}
+
+static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
+{
+ int ret;
+
+ ret = clk_prepare_enable(sp->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc1);
+ if (ret)
+ return ret;
+
return 0;
}

@@ -920,7 +957,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
if (ret)
return ret;

- ret = clk_prepare_enable(sp->clk);
+ ret = cdns_sierra_phy_enable_clocks(sp);
if (ret)
return ret;

--
2.17.1
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