[lkml]   [2020]   [Oct]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
Subject[PATCH V3 0/2] Add support to configure DWC for ECRC
This series has two patches.

Patch-1: Adds a public API to query if the system has ECRC policty turned on.

Patch-2: DesignWare core PCIe IP has a TLP Digest (TD) override bit in one of
its control registers of ATU. This bit needs to be programmed for proper ECRC
functionality. This is currently identified as an issue with DesignWare
IP version 4.90a. DWC code queries the PCIe sub-system through the API added
in Patch-1 to find out if ECRC is turned on or not and configures ATU

* Addressed Ethan Zhao's comments for patch-1

* Addressed Jingoo's review comments

Vidya Sagar (2):
PCI/AER: Add pcie_is_ecrc_enabled() API
PCI: dwc: Add support to configure for ECRC

drivers/pci/controller/dwc/pcie-designware.c | 8 ++++++--
drivers/pci/controller/dwc/pcie-designware.h | 1 +
drivers/pci/pci.h | 2 ++
drivers/pci/pcie/aer.c | 11 +++++++++++
4 files changed, 20 insertions(+), 2 deletions(-)


 \ /
  Last update: 2020-10-29 09:39    [W:0.159 / U:0.064 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site