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Subject[PATCH v6 21/21] perf arm-spe: Add support for ARMv8.3-SPE
Date
From: Wei Li <liwei391@huawei.com>

This patch is to support Armv8.3 extension for SPE, it adds alignment
field in the Events packet and it supports the Scalable Vector Extension
(SVE) for Operation packet and Events packet with two additions:

- The vector length for SVE operations in the Operation Type packet;
- The incomplete predicate and empty predicate fields in the Events
packet.

Signed-off-by: Wei Li <liwei391@huawei.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm-spe-decoder/arm-spe-pkt-decoder.c | 39 ++++++++++++++++++-
.../arm-spe-decoder/arm-spe-pkt-decoder.h | 16 ++++++++
2 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
index 9ec3057de86f..52c4990885ae 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c
@@ -304,6 +304,12 @@ static int arm_spe_pkt_desc_event(const struct arm_spe_pkt *packet,
arm_spe_pkt_snprintf(&err, &buf, &blen, " LLC-REFILL");
if (payload & BIT(EV_REMOTE_ACCESS))
arm_spe_pkt_snprintf(&err, &buf, &blen, " REMOTE-ACCESS");
+ if (payload & BIT(EV_ALIGNMENT))
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " ALIGNMENT");
+ if (payload & BIT(EV_PARTIAL_PREDICATE))
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " SVE-PARTIAL-PRED");
+ if (payload & BIT(EV_EMPTY_PREDICATE))
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " SVE-EMPTY-PRED");

return err ?: (int)(buf_len - blen);
}
@@ -317,8 +323,26 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet,

switch (packet->index) {
case SPE_OP_PKT_HDR_CLASS_OTHER:
- return arm_spe_pkt_snprintf(&err, &buf, &blen,
- payload & SPE_OP_PKT_COND ? "COND-SELECT" : "INSN-OTHER");
+ if (SPE_OP_PKT_IS_OTHER_SVE_OP(payload)) {
+ arm_spe_pkt_snprintf(&err, &buf, &blen, "SVE-OTHER");
+
+ /* SVE effective vector length */
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " EVLEN %d",
+ SPE_OP_PKG_SVE_EVL(payload));
+
+ if (payload & SPE_OP_PKT_SVE_FP)
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " FP");
+ if (payload & SPE_OP_PKT_SVE_PRED)
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " PRED");
+ } else {
+ arm_spe_pkt_snprintf(&err, &buf, &blen, "OTHER");
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " %s",
+ payload & SPE_OP_PKT_COND ?
+ "COND-SELECT" : "INSN-OTHER");
+ }
+
+ return err ?: (int)(buf_len - blen);
+
case SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC:
arm_spe_pkt_snprintf(&err, &buf, &blen,
payload & 0x1 ? "ST" : "LD");
@@ -349,6 +373,17 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet,
break;
}

+ if (SPE_OP_PKT_IS_LDST_SVE(payload)) {
+ /* SVE effective vector length */
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " EVLEN %d",
+ SPE_OP_PKG_SVE_EVL(payload));
+
+ if (payload & SPE_OP_PKT_SVE_PRED)
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " PRED");
+ if (payload & SPE_OP_PKT_SVE_SG)
+ arm_spe_pkt_snprintf(&err, &buf, &blen, " SG");
+ }
+
return err ?: (int)(buf_len - blen);

case SPE_OP_PKT_HDR_CLASS_BR_ERET:
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
index 1ad14885c2a1..9b970e7bf1e2 100644
--- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
+++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h
@@ -113,6 +113,8 @@ enum arm_spe_events {
#define SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC 0x1
#define SPE_OP_PKT_HDR_CLASS_BR_ERET 0x2

+#define SPE_OP_PKT_IS_OTHER_SVE_OP(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
+
#define SPE_OP_PKT_COND BIT(0)

#define SPE_OP_PKT_LDST_SUBCLASS_GET(v) ((v) & GENMASK_ULL(7, 1))
@@ -128,6 +130,20 @@ enum arm_spe_events {
#define SPE_OP_PKT_AT BIT(2)
#define SPE_OP_PKT_ST BIT(0)

+#define SPE_OP_PKT_IS_LDST_SVE(v) (((v) & (BIT(3) | BIT(1))) == 0x8)
+
+#define SPE_OP_PKT_SVE_SG BIT(7)
+/*
+ * SVE effective vector length (EVL) is stored in byte 0 bits [6:4];
+ * the length is rounded up to a power of two and use 32 as one step,
+ * so EVL calculation is:
+ *
+ * 32 * (2 ^ bits [6:4]) = 32 << (bits [6:4])
+ */
+#define SPE_OP_PKG_SVE_EVL(v) (32 << (((v) & GENMASK_ULL(6, 4)) >> 4))
+#define SPE_OP_PKT_SVE_PRED BIT(2)
+#define SPE_OP_PKT_SVE_FP BIT(1)
+
#define SPE_OP_PKT_IS_INDIRECT_BRANCH(v) (((v) & GENMASK_ULL(7, 1)) == 0x2)

const char *arm_spe_pkt_name(enum arm_spe_pkt_type);
--
2.17.1
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