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SubjectRe: [PATCH 1/1] clk: aspeed: modify some default clks are critical
Quoting Joel Stanley (2020-10-13 22:28:00)
> On Wed, 14 Oct 2020 at 02:50, Stephen Boyd <> wrote:
> >
> > Quoting Ryan Chen (2020-09-28 00:01:08)
> > > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> > > default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> > > eSPI slave channel, those clks can't be disable should keep default,
> > > otherwise will affect Host side access SuperIO and SPI slave device.
> > >
> > > Signed-off-by: Ryan Chen <>
> > > ---
> >
> > Is there resolution on this thread?
> Not yet.
> We have a system where the BMC (management controller) controls some
> clocks, but the peripherals that it's clocking are outside the BMC's
> control. In this case, the host processor us using some UARTs and what
> not independent of any code running on the BMC.
> Ryan wants to have them marked as critical so the BMC never powers them down.
> However, there are systems that don't use this part of the soc, so for
> those implementations they are not critical and Linux on the BMC can
> turn them off.
> Do you have any thoughts? Has anyone solved a similar problem already?

Is this critical clocks in DT? Where we want to have different DT for
different device configurations to indicate that some clks should be
marked critical so they're never turned off and other times they aren't
so they're turned off?

It also sounds sort of like the protected-clocks binding. Where you
don't want to touch certain clks depending on the usage configuration of
the SoC. There is a patch to make that generic that I haven't applied
because it looks wrong at first glance[1]. Maybe not registering those
clks to the framework on the configuration that Ryan has is good enough?


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