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SubjectRe: [PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
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Quoting Paul Cercueil (2020-09-02 18:50:46)
> CLK_SET_RATE_GATE means that the clock must be gated when being
> reclocked. This is not the case for the PLLs in Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---

Applied to clk-next

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