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SubjectRe: [PATCH 2/2] clk: axi-clkgen: Set power bits for fractional mode
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Quoting Alexandru Ardelean (2020-10-01 01:59:48)
> From: Lars-Peter Clausen <lars@metafoo.de>
>
> Using the fractional dividers requires some additional power bits to be
> set.
>
> The fractional power bits are not documented and the current heuristic
> for setting them seems be insufficient for some cases. Just always set all
> the fractional power bits when in fractional mode.
>
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---

Applied to clk-next

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