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SubjectRe: [PATCH 1/2] clk: axi-clkgen: Add support for fractional dividers
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Quoting Alexandru Ardelean (2020-10-01 01:59:47)
> From: Lars-Peter Clausen <lars@metafoo.de>
>
> The axi-clkgen has (optional) fractional dividers on the output clock
> divider and feedback clock divider path. Utilizing the fractional dividers
> allows for a better resolution of the output clock, being able to
> synthesize more frequencies.
>
> Rework the driver support to support the fractional register fields, both
> for setting a new rate as well as reading back the current rate from the
> hardware.
>
> For setting the rate if no perfect divider settings were found in
> non-fractional mode try again in fractional mode and see if better settings
> can be found. This appears to be the recommended mode of operation.
>
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---

Applied to clk-next

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