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Subject[PATCH v4 4/4] interconnect: qcom: Add OSM L3 support on SC7180
Date
Add Operating State Manager (OSM) L3 interconnect provider support on
SC7180 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/interconnect/qcom/osm-l3.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)

diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 7fde53c70081e..df2cec3fa2913 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -28,6 +28,7 @@

#define OSM_L3_MAX_LINKS 1
#define SDM845_MAX_RSC_NODES 130
+#define SC7180_MAX_RSC_NODES 137

#define to_qcom_provider(_provider) \
container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
@@ -37,6 +38,11 @@ enum {
SDM845_SLAVE_OSM_L3,
};

+enum {
+ SC7180_MASTER_OSM_L3_APPS = SC7180_MAX_RSC_NODES + 1,
+ SC7180_SLAVE_OSM_L3,
+};
+
struct qcom_osm_l3_icc_provider {
void __iomem *base;
unsigned int max_state;
@@ -87,6 +93,19 @@ static struct qcom_icc_desc sdm845_icc_osm_l3 = {
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
};

+DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
+DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
+
+static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
+ [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
+ [SLAVE_OSM_L3] = &sc7180_osm_l3,
+};
+
+static struct qcom_icc_desc sc7180_icc_osm_l3 = {
+ .nodes = sc7180_osm_l3_nodes,
+ .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
+};
+
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_osm_l3_icc_provider *qp;
@@ -248,6 +267,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
}

static const struct of_device_id osm_l3_of_match[] = {
+ { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ },
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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