Messages in this thread |  | | From | Martin Blumenstingl <> | Date | Tue, 7 Jan 2020 15:01:13 +0100 | Subject | Re: [RFC v1 0/2] dwmac-meson8b Ethernet RX delay configuration |
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Hello Jianxin,
On Thu, Dec 26, 2019 at 9:37 PM Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote: > > The Ethernet TX performance has been historically bad on Meson8b and > Meson8m2 SoCs because high packet loss was seen. I found out that this > was related (yet again) to the RGMII TX delay configuration. > In the process of discussing the big picture (and not just a single > patch) [0] with Andrew I discovered that the IP block behind the > dwmac-meson8b driver actually seems to support the configuration of the > RGMII RX delay (at least on the Meson8b SoC generation). > > The goal of this series is to start the discussion around how to > implement the RGMII RX delay on this IP block. Additionally it seems > that the RX delay can also be applied for RMII PHYs? > > @Jianxin: can you please add the Amlogic internal Ethernet team to this > discussion? My questions are documented in the patch description of > patch #2. do you already have an update for me on this topic?
while we're discussing unknown bits of the Ethernet controller I also remembered that we're currently not describing the relation between the "fclk_div2" clock and the Ethernet controller. however, as described in commit 72e1f230204039 ("clk: meson: meson8b: mark fclk_div2 gate clocks as CLK_IS_CRITICAL") this is needed for RGMII mode. it would be great to know the relation between fclk_div2 and RGMII mode on the Ethernet controller!
Thank you! Martin
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