Messages in this thread |  | | From | Anup Patel <> | Date | Wed, 8 Jan 2020 09:06:38 +0530 | Subject | Re: [PATCH v2] riscv: to make sure the cores in .Lsecondary_park |
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On Wed, Jan 8, 2020 at 8:10 AM Greentime Hu <greentime.hu@sifive.com> wrote: > > The code in secondary_park is currently placed in the .init section. The > kernel reclaims and clears this code when it finishes booting. That > causes the cores parked in it to go to somewhere unpredictable, so we > move this function out of init to make sure the cores stay looping there. > > Signed-off-by: Greentime Hu <greentime.hu@sifive.com> > --- > arch/riscv/kernel/head.S | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index f8f996916c5b..276b98f9d0bd 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -217,11 +217,6 @@ relocate: > tail smp_callin > #endif > > -.align 2 > -.Lsecondary_park: > - /* We lack SMP support or have too many harts, so park this hart */ > - wfi > - j .Lsecondary_park > END(_start) > > #ifdef CONFIG_RISCV_M_MODE > @@ -303,6 +298,13 @@ ENTRY(reset_regs) > END(reset_regs) > #endif /* CONFIG_RISCV_M_MODE */ > > +.section ".text", "ax",@progbits > +.align 2 > +.Lsecondary_park: > + /* We lack SMP support or have too many harts, so park this hart */ > + wfi > + j .Lsecondary_park > + > __PAGE_ALIGNED_BSS > /* Empty zero page */ > .balign PAGE_SIZE > -- > 2.17.1 >
LGTM.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards, Anup
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