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SubjectRe: [PATCH v6 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
From
Date
Hi,

On 30/12/19 1:11 pm, Ramuthevar,Vadivel MuruganX wrote:
[...]
> +static u32 cqspi_cmd2addr(const unsigned char *addr_buf, u32 addr_width)
> +{
> + unsigned int addr = 0;
> + int i;
> +
> + /* Invalid address return zero. */
> + if (addr_width > 4)
> + return 0;
> +
> + for (i = 0; i < addr_width; i++) {
> + addr = addr << 8;
> + addr |= addr_buf[i];
> + }
> +
> + return addr;
> +}
> +
[...]
> +static int cqspi_apb_read_setup(struct struct_cqspi *cqspi,
> + const struct spi_mem_op *op,
> + const u8 *addrbuf)
> +{
> + void __iomem *reg_base = cqspi->iobase;
> + size_t addrlen = op->addr.nbytes;
> + size_t dummy_bytes = op->dummy.nbytes;
> + unsigned int addr_value, dummy_clk, reg;
> +
> + if (addrlen) {
> + addr_value = cqspi_cmd2addr(&addrbuf[0], addrlen);
> + writel(addr_value, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
> + }
> +

Why do you need to swap the address bytes to SPI bus order? You are
writing to a controller register that accepts 24 bit or 32 bit address.

> + reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
> + reg |= (op->data.buswidth & CQSPI_REG_RD_INSTR_TYPE_DATA_MASK) <<
> + CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
> +

This is wrong... op->data.buswidth's range is 1 to 8 whereas
CQSPI_REG_RD_INSTR_TYPE range is 0 to 3. I wonder whether you tested
dual/quad mode with this driver?

I am still unable to get this series to work on my platform. Will
continue to debug...

--
Regards
Vignesh

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