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    Subject[PATCH 4.19 411/639] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register
    Date
    From: Ondrej Jirman <megous@megous.com>

    [ Upstream commit f167675486c37b88620d344fbb12d06e34f11d47 ]

    The current code defines W1 clock gate to be at 0x1cc, overlaying it
    with the IR gate.

    Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
    causing interrupt floods on H6 (because interrupt flags can't be cleared,
    due to IR module's bus being disabled).

    Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
    Signed-off-by: Ondrej Jirman <megous@megous.com>
    Acked-by: Clément Péron <peron.clem@gmail.com>
    Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
    index 27554eaf69298..8d05d4f1f8a1e 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
    @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
    static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
    0x1cc, BIT(0), 0);
    static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
    - 0x1cc, BIT(0), 0);
    + 0x1ec, BIT(0), 0);

    /* Information of IR(RX) mod clock is gathered from BSP source code */
    static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
    --
    2.20.1


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