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SubjectRe: [PATCH v2 01/14] dt-bindings: PCI: cadence: Add PCIe RC/EP DT schema for Cadence PCIe
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hi Rob,

On 08/01/20 11:05 AM, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 08/01/20 9:13 AM, Rob Herring wrote:
>> On Mon, Jan 06, 2020 at 03:50:45PM +0530, Kishon Vijay Abraham I wrote:
>>> Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence
>>> PCIe core library. Platforms using Cadence PCIe core can include the
>>> schemas added here in the platform specific schemas.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>> ---
>>> .../devicetree/bindings/pci/cdns-pcie-ep.yaml | 20 ++++++++++++
>>> .../bindings/pci/cdns-pcie-host.yaml | 30 +++++++++++++++++
>>> .../devicetree/bindings/pci/cdns-pcie.yaml | 32 +++++++++++++++++++
>>> 3 files changed, 82 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
>>> create mode 100644 Documentation/devicetree/bindings/pci/cdns-pcie.yaml
>>
>> Need to remove the old files.
>>
>> Note that I posted a conversion of Cadence host[1]. Yours goes further,
>> but please compare and add anything mine has that yours doesn't.
>>
>> [1] https://lore.kernel.org/linux-pci/20191231193903.15929-2-robh@kernel.org/
>
> Sure, I'll look at this.
>
> Recently we converted Cadence driver to a library since the same Cadence
> core can be used by multiple vendors. Here I'm trying to add the
> bindings for Cadence core which can be included in the platform specific
> schema.
>
> So the existing cdns,cdns-pcie-host.yaml which is a Cadence platform
> using Cadence core should include cdns-pcie-host.yaml.
>
> "[PATCH v2 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's
> J721E SoC" in this series includes "cdns-pcie-host.yaml" for TI platform
> using Cadence core.
>
> That's why in the schema added here you don't see the compatible since
> that will be added in platform specific schema.

Does this approach look fine to you?

Thanks
Kishon

>>
>>>
>>> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
>>> new file mode 100644
>>> index 000000000000..36aaae5931c3
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml
>>> @@ -0,0 +1,20 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
>>> +%YAML 1.2
>>> +--
>>> +$id: "http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Cadence PCIe Endpoint
>>> +
>>> +maintainers:
>>> + - Tom Joseph <tjoseph@cadence.com>
>>> +
>>> +allOf:
>>> + - $ref: "cdns-pcie.yaml#"
>>> +
>>> +properties:
>>> + max-functions:
>>> + description: Maximum number of functions that can be configured (default 1)
>>> + allOf:
>>> + - $ref: /schemas/types.yaml#/definitions/uint8
>>> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
>>> new file mode 100644
>>> index 000000000000..78261bc4f0c5
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml
>>> @@ -0,0 +1,30 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Cadence PCIe Host
>>> +
>>> +maintainers:
>>> + - Tom Joseph <tjoseph@cadence.com>
>>> +
>>> +allOf:
>>> + - $ref: "/schemas/pci/pci-bus.yaml#"
>>> + - $ref: "cdns-pcie.yaml#"
>>> +
>>> +properties:
>>> + vendor-id:
>>> + description: The PCI vendor ID (16 bits, default is design dependent)
>>> +
>>> + device-id:
>>> + description: The PCI device ID (16 bits, default is design dependent)
>>
>> While these got defined here as 16-bits, these should be fixed to 32-bit
>> because they are established properties for a long time.
>>
>>> +
>>> + cdns,no-bar-match-nbits:
>>> + description: Set into the no BAR match register to configure the number
>>> + of least significant bits kept during inbound (PCIe -> AXI) address
>>> + translations (default 32)
>>> + allOf:
>>> + - $ref: /schemas/types.yaml#/definitions/uint32
>>
>> What about compatible?
>>
>>> +
>>> diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml
>>> new file mode 100644
>>> index 000000000000..497d3dc2e6f2
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pci/cdns-pcie.yaml
>>> @@ -0,0 +1,32 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
>>> +%YAML 1.2
>>> +---
>>> +$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
>>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>>> +
>>> +title: Cadence PCIe Core
>>> +
>>> +maintainers:
>>> + - Tom Joseph <tjoseph@cadence.com>
>>> +
>>> +properties:
>>> + max-link-speed:
>>> + minimum: 1
>>> + maximum: 3
>>> +
>>> + num-lanes:
>>> + minimum: 1
>>> + maximum: 2
>>
>> Needs a type.
>>
>> The Cadence IP can't support x4, x8, or x16?
>
> I'll fix this. I assume these can be overwritten in platform specific
> schema files?
>
> Thanks
> Kishon
>

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