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SubjectRe: [PATCH v2] arm64: cpufeature: Export matrix and other features to userspace
On Wed, Jan 15, 2020 at 09:49:17AM +0000, Will Deacon wrote:
> On Mon, Dec 16, 2019 at 11:33:37AM +0000, Steven Price wrote:
> > Export the features introduced as part of ARMv8.6 exposed in the
> > ID_AA64ISAR1_EL1 and ID_AA64ZFR0_EL1 registers. This introduces the
> > Matrix features (ARMv8.2-I8MM, ARMv8.2-F64MM and ARMv8.2-F32MM) along
> > with BFloat16 (Armv8.2-BF16), speculation invalidation (SPECRES) and
> > Data Gathering Hint (ARMv8.0-DGH).
> >
> > Signed-off-by: Julien Grall <julien.grall@arm.com>
> > [Added other features in those registers]
> > Signed-off-by: Steven Price <steven.price@arm.com>
> > ---
> > This is a v2 of Julien's patch[1] extended to export all the new
> > features contained within the ID_AA64ISAR1_EL1 and ID_AA64ZFR0_EL1
> > registers.
> >
> > [1] https://lore.kernel.org/linux-arm-kernel/20191025171056.30641-1-julien.grall@arm.com/
> >
> > Documentation/arm64/cpu-feature-registers.rst | 16 ++++++++++
> > Documentation/arm64/elf_hwcaps.rst | 31 +++++++++++++++++++
> > arch/arm64/include/asm/hwcap.h | 8 +++++
> > arch/arm64/include/asm/sysreg.h | 12 +++++++
> > arch/arm64/include/uapi/asm/hwcap.h | 8 +++++
> > arch/arm64/kernel/cpufeature.c | 20 ++++++++++++
> > arch/arm64/kernel/cpuinfo.c | 8 +++++
> > 7 files changed, 103 insertions(+)
> >
> > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst
> > index b6e44884e3ad..5382981533f8 100644
> > --- a/Documentation/arm64/cpu-feature-registers.rst
> > +++ b/Documentation/arm64/cpu-feature-registers.rst
> > @@ -200,6 +200,14 @@ infrastructure:
> > +------------------------------+---------+---------+
> > | Name | bits | visible |
> > +------------------------------+---------+---------+
> > + | I8MM | [55-52] | y |
> > + +------------------------------+---------+---------+
> > + | DGH | [51-48] | y |
> > + +------------------------------+---------+---------+
> > + | BF16 | [47-44] | y |
> > + +------------------------------+---------+---------+
> > + | SPECRES | [43-40] | y |
> > + +------------------------------+---------+---------+
>
> I applied this for CI testing last night, but actually I think it's broken.
> AFAICT, the instructions introduced by SPECRES are behind an SCTLR_EL1
> enable (EnRCTX) which defaults to disabled, so we should either be enabling
> them before setting the HWCAP or not exposing them at all.
>
> Given that the instructions are not broadcast and are likely to be very
> expensive, I don't think that exposing them to EL0 is a good idea.
>
> In other words, I'll drop the SPECRES parts from this patch. Sound ok?

I completely agree. We deliberately avoided adding SPECRES for those
reasons previously:

https://lore.kernel.org/r/20191212144633.GE46910@lakrids.cambridge.arm.com

Thanks,
Mark.

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