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Subject[PATCH v3 0/2] cacheinfo support to read no. of L2 cache ways enabled
The patchset includes 2 patches. Patch 1 implements cache_get_priv_group
which make use of a generic ops structure to return a private attribute
group for custom cacheinfo. Patch 2 implements a private attribute named
"number_of_ways_enabled" in the cacheinfo framework. Reading this
attribute returns the number of L2 cache ways enabled at runtime,

This patchset is based on Linux v5.5-rc6 and tested on HiFive Unleashed

v3 vs v2:
- As per Anup Patel's suggestion[0], implement a new approach which uses
generic ops structure. Hence addition of patch 1 to this series and
corresponding changes to patch 2.
- Dropped "riscv: dts: Add DT support for SiFive L2 cache controller"
patch since it is already merged
- Rebased on Linux v5.5-rc6

Changes in v2:
- Rebase the series on v5.5-rc3
- Remove the reserved-memory node from DT

Yash Shah (2):
riscv: cacheinfo: Implement cache_get_priv_group with a generic ops
riscv: Add support to determine no. of L2 cache way enabled

arch/riscv/include/asm/cacheinfo.h | 15 ++++++++++++++
arch/riscv/kernel/cacheinfo.c | 17 ++++++++++++++++
drivers/soc/sifive/sifive_l2_cache.c | 38 ++++++++++++++++++++++++++++++++++++
include/soc/sifive/sifive_l2_cache.h | 2 ++
4 files changed, 72 insertions(+)
create mode 100644 arch/riscv/include/asm/cacheinfo.h


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