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SubjectRe: [PATCH v13 0/8] Exynos5 Dynamic Memory Controller driver

On 9/4/19 8:40 PM, Krzysztof Kozlowski wrote:
> On Wed, Aug 21, 2019 at 12:42:55PM +0200, Lukasz Luba wrote:
>> Hi all,
>> This is v13 which makes cosmetic changes. It is based on current mainline
>> (v5.3-rc5) with with devfreq/for-next where there is a PPMU patch [1].
>> The patch set adds support of Dynamic Memory Controller for Exynos5422 SoC.
>> The driver supports Dynamic Voltage and Frequency Scaling
>> for the DMC and DRAM. It also provides needed timings for different
>> speed operations of the DRAM memory.
>> There is also new generic code in of_memory and headers which allows to parse
>> LPDDR3 memories defined in device-tree.
>> Here are the last changes suggested by Krzysztof during his review.
>> For the previous changes in older revisions please refer to [2], there is
>> more detailed change log.
>> changes:
>> v13:
>> - skipped patch with chipID changes in DT, since it is not used anymore,
>> - removed license comment in of_memory.c since SPDX has been merged,
>> - aligned comment to the current fields in the structure,
>> - changed printed warning when timings are not found,
>> Regards,
>> Lukasz Luba
>> [1]
>> [2]
> Thanks, applied entire set (except last defconfig patch) to two topic
> branches, either for v5.4 or for v5.5 (it is quite late). I'll take the
> last defconfig separately.
> Automated tools found few issues to fix, please send incremental
> patches.
OK, there will be around 3 patches with fixes.
> In general, for new drivers always run automated checks - Smatch and
> Sparse. Coccinelle is also recommended. Checkpatch pointed missing
> compatible documentation - need to be fixed (see
> as an example).
As I have responded in my previous email, I ignored it since Elpida
lpddr2 does not have bindings documentation. I will create the needed
documentation file in the follow up patch.


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