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Subject[PATCH v1] ARM: dts: realtek: Add support for Realtek evaluation
Date
From: "james.tai" <james.tai@realtek.com>

This patch adds a generic devicetree board file and a dtsi for
Realtek RTD16XX and RTD13XX platform.

Signed-off-by: james.tai <james.tai@realtek.com>
---
Changes since last version:
- Add RTD13XX platform.
- Add PSCI support.
- Add aliases.
- move uart0 to dtsi file.
---
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/rtd1319-pymparticle.dts | 30 ++++++
arch/arm/boot/dts/rtd13xx.dtsi | 105 +++++++++++++++++++
arch/arm/boot/dts/rtd1619-mjolnir.dts | 31 ++++++
arch/arm/boot/dts/rtd16xx.dtsi | 119 ++++++++++++++++++++++
5 files changed, 289 insertions(+)
create mode 100644 arch/arm/boot/dts/rtd1319-pymparticle.dts
create mode 100644 arch/arm/boot/dts/rtd13xx.dtsi
create mode 100644 arch/arm/boot/dts/rtd1619-mjolnir.dts
create mode 100644 arch/arm/boot/dts/rtd16xx.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2cea90..c401184622cd 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -927,6 +927,9 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-pinky.dtb \
rk3288-veyron-speedy.dtb \
rk3288-vyasa.dtb
+ dtb-$(CONFIG_ARCH_REALTEK) += \
+ rtd1619-mjolnir.dtb \
+ rtd1319-pymparticle.dtb
dtb-$(CONFIG_ARCH_S3C24XX) += \
s3c2416-smdk2416.dtb
dtb-$(CONFIG_ARCH_S3C64XX) += \
@@ -1286,3 +1289,4 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-bmc-opp-zaius.dtb \
aspeed-bmc-portwell-neptune.dtb \
aspeed-bmc-quanta-q71l.dtb
+
diff --git a/arch/arm/boot/dts/rtd1319-pymparticle.dts b/arch/arm/boot/dts/rtd1319-pymparticle.dts
new file mode 100644
index 000000000000..887ab894bba1
--- /dev/null
+++ b/arch/arm/boot/dts/rtd1319-pymparticle.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd13xx.dtsi"
+
+/ {
+ model= "Realtek Pymparticle Evaluation Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,460800 earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/rtd13xx.dtsi b/arch/arm/boot/dts/rtd13xx.dtsi
new file mode 100644
index 000000000000..9a565919ab83
--- /dev/null
+++ b/arch/arm/boot/dts/rtd13xx.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/{
+ compatible = "realtek,rtd1319";
+ interrupt-parent = <&gic>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x000>;
+ next-level-cache = <&a55_l2>;
+ };
+
+ A55_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ A55_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ A55_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+
+ a55_l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 8)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 8)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 8)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 8)>;
+ clock-frequency = <27000000>;
+ };
+
+ osc27M: osc27M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "osc27M";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@ff100000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ redistributor-stride = <0x0 0x20000>;
+ #redistributor-regions = <1>;
+ reg = <0x0 0xff100000 0x0 0x10000>, /* GICD */
+ <0x0 0xff140000 0x0 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9 4>;
+ };
+
+ uart0: serial0@98007800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x98007800 0x0 0x400>,
+ <0x0 0x98007000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <0 68 4>;
+ clock-frequency = <432000000>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rtd1619-mjolnir.dts b/arch/arm/boot/dts/rtd1619-mjolnir.dts
new file mode 100644
index 000000000000..3157c8cd5430
--- /dev/null
+++ b/arch/arm/boot/dts/rtd1619-mjolnir.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
+/dts-v1/;
+
+#include "rtd16xx.dtsi"
+
+/ {
+ model= "Realtek Mjolnir Evaluation Board";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 earlycon";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/rtd16xx.dtsi b/arch/arm/boot/dts/rtd16xx.dtsi
new file mode 100644
index 000000000000..f18726086746
--- /dev/null
+++ b/arch/arm/boot/dts/rtd16xx.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/*
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/{
+ compatible = "realtek,rtd1619";
+ interrupt-parent = <&gic>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x000>;
+ next-level-cache = <&a55_l2>;
+ };
+
+ A55_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+
+ A55_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ };
+
+ A55_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ };
+
+ A55_4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x400>;
+ enable-method = "psci";
+ };
+
+ A55_5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55", "arm,armv8";
+ reg = <0x500>;
+ enable-method = "psci";
+ };
+
+ a55_l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 8)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 8)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 8)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 8)>;
+ clock-frequency = <27000000>;
+ };
+
+ osc27M: osc27M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names = "osc27M";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@ff100000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ redistributor-stride = <0x0 0x20000>;
+ #redistributor-regions = <1>;
+ reg = <0x0 0xff100000 0x0 0x10000>, /* GICD */
+ <0x0 0xff140000 0x0 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9 4>;
+ };
+
+ uart0: serial0@98007800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x98007800 0x0 0x400>,
+ <0x0 0x98007000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <0 68 4>;
+ clock-frequency = <27000000>;
+ status = "disabled";
+ };
+ };
+};
--
2.17.1
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