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SubjectRe: [PATCH v22 02/24] x86/cpufeatures: x86/msr: Intel SGX Launch Control hardware bits
On Wed, Sep 25, 2019 at 05:19:49PM +0200, Borislav Petkov wrote:
> On Wed, Sep 25, 2019 at 05:09:03PM +0300, Jarkko Sakkinen wrote:
> > The driver will support only the case where the bit is set i.e. that
> > it can freely write to the MSRs MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}.
> > It will refuse to initialize otherwise.
> See this:
> AFAICT, when FEATURE_CONTROL_SGX_LE_WR is not set, you're not clearing
> all SGX feature bits. But you should, methinks.

Correct, only X86_FEATURE_SGX_LC is cleared. The idea is to have SGX_LC
reflect whether or not flexible launch control is fully enabled, no more
no less.

Functionally, this doesn't impact support for native enclaves as the
driver will refuse to load if SGX_LC=0.

Looking forward, this *will* affect KVM. As proposed, KVM would expose
SGX to a guest regardless of SGX_LC support.

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