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SubjectRe: [PATCH v22 02/24] x86/cpufeatures: x86/msr: Intel SGX Launch Control hardware bits
On Tue, Sep 03, 2019 at 05:26:33PM +0300, Jarkko Sakkinen wrote:
> From: Kai Huang <kai.huang@linux.intel.com>
>
> Add X86_FEATURE_SGX_LC, which informs whether or not the CPU supports SGX
> Launch Control.
>
> Add MSR_IA32_SGXLEPUBKEYHASH{0, 1, 2, 3}, which when combined contain a
> SHA256 hash of a 3072-bit RSA public key. SGX backed software packages, so
> called enclaves, are always signed. All enclaves signed with the public key
> are unconditionally allowed to initialize. [1]
>
> Add FEATURE_CONTROL_SGX_LE_WR bit of the feature control MSR, which informs
> whether the formentioned MSRs are writable or not. If the bit is off, the
> public key MSRs are read-only for the OS.
>
> If the MSRs are read-only, the platform must provide a launch enclave (LE).
> LE can create cryptographic tokens for other enclaves that they can pass
> together with their signature to the ENCLS(EINIT) opcode, which is used
> to initialize enclaves.
>
> Linux is unlikely to support the locked configuration because it takes away
> the control of the launch decisions from the kernel.

Right, who has control over FEATURE_CONTROL_SGX_LE_WR? Can the
kernel set it and put another hash in there or there will be locked
configurations where setting that bit will trap?

I don't want to leave anything in the hands of the BIOS controlling
whether the platform can set its own key because BIOS is known to f*ck
it up almost every time. And so I'd like for us to be able to fix up
things without depending on the mood of some OEM vendor's BIOS fixing
desire.

> [1] Intel SDM: 38.1.4 Intel SGX Launch Control Configuration
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
> Co-developed-by: Haim Cohen <haim.cohen@intel.com>
> Signed-off-by: Haim Cohen <haim.cohen@intel.com>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>

This time checkpatch is right:

WARNING: Missing Signed-off-by: line by nominal patch author 'Kai Huang <kai.huang@linux.intel.com>'

And looking at the SOB chain, sounds like people need to make up their
mind about authorship...

> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> arch/x86/include/asm/msr-index.h | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index c5582e766121..ca82226e25ec 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -355,6 +355,7 @@
> #define X86_FEATURE_CLDEMOTE (16*32+25) /* CLDEMOTE instruction */
> #define X86_FEATURE_MOVDIRI (16*32+27) /* MOVDIRI instruction */
> #define X86_FEATURE_MOVDIR64B (16*32+28) /* MOVDIR64B instruction */
> +#define X86_FEATURE_SGX_LC (16*32+30) /* Software Guard Extensions Launch Control */

Amazing. SGX feature bits are spread around at least three CPUID leafs:

7_EBX, 7_ECX, 12_EAX. Maybe there's a 4th somewhere because hey... :-\

--
Regards/Gruss,
Boris.

https://people.kernel.org/tglx/notes-about-netiquette

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