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SubjectRe: [PATCH v2 1/2] clk: tegra: divider: Add missing check for enable-bit on rate's recalculation
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23.07.2019 5:52, Dmitry Osipenko пишет:
> Unset "enable" bit means that divider is in bypass mode, hence it doesn't
> have any effect in that case. Please note that there are no known bugs
> caused by the missing check.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>
> Changelog:
>
> v2: Changed the commit's description from 'Fix' to 'Add' in response to the
> Stephen's Boyd question about the need to backport the patch into stable
> kernels. The backporting is not really needed.
>
> drivers/clk/tegra/clk-divider.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index e76731fb7d69..f33c19045386 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
> int div, mul;
> u64 rate = parent_rate;
>
> - reg = readl_relaxed(divider->reg) >> divider->shift;
> - div = reg & div_mask(divider);
> + reg = readl_relaxed(divider->reg);
> +
> + if ((divider->flags & TEGRA_DIVIDER_UART) &&
> + !(reg & PERIPH_CLK_UART_DIV_ENB))
> + return rate;
> +
> + div = (reg >> divider->shift) & div_mask(divider);
>
> mul = get_mul(divider);
> div += mul;
>

Hello Peter,

ACK?

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