lkml.org 
[lkml]   [2019]   [Aug]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [alsa-devel] [RFC PATCH 27/40] soundwire: Add Intel resource management algorithm
From
Date

>> +static int sdw_select_row_col(struct sdw_bus *bus, int clk_freq)
>> +{
>> + struct sdw_master_prop *prop = &bus->prop;
>> + int frame_int, frame_freq;
>> + int r, c;
>> +
>> + for (c = 0; c < SDW_FRAME_COLS; c++) {
>> + for (r = 0; r < SDW_FRAME_ROWS; r++) {
>> + if (sdw_rows[r] != prop->default_row ||
>> + sdw_cols[c] != prop->default_col)
>> + continue;
>
> Are we only supporting default rows and cols?

for now yes. Note that the default is defined by firmware and e.g.
different for ICL (50x4) and CML (125x2). The firmware itself also
provides a single clock value so we'd need to override the DSDT or force
the properties to be different to use multiple gears.

This will probably change at some point when we have multiple device per
link. SoundWire 1.2 devices also provide a standard means to control the
clock, otherwise with SoundWire 1.1 the clock management requires quite
a bit of imp-def changes that we have not tested.

>
>> +
>> + frame_int = sdw_rows[r] * sdw_cols[c];
>> + frame_freq = clk_freq / frame_int;
>> +
>> + if ((clk_freq - (frame_freq * SDW_FRAME_CTRL_BITS)) <
>> + bus->params.bandwidth)
>> + continue;
>> +
>> + bus->params.row = sdw_rows[r];
>> + bus->params.col = sdw_cols[c];
>> + return 0;
>> + }
>> + }
>> +
>> + return -EINVAL;
>> +}
>> +
>> --
>> 2.20.1
>>
>

\
 
 \ /
  Last update: 2019-08-05 21:10    [W:0.124 / U:12.076 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site