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SubjectRe: [RESEND PATCH V3 1/8] perf/x86/intel: Set correct mask for TOPDOWN.SLOTS
On Mon, Aug 26, 2019 at 07:47:33AM -0700, kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
>
> TOPDOWN.SLOTS(0x0400) is not a generic event. It is only available on
> fixed counter3.
>
> Don't extend its mask to generic counters.
>
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>


> diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
> index 1392d5e6e8d6..457d35a75ad3 100644
> --- a/arch/x86/include/asm/perf_event.h
> +++ b/arch/x86/include/asm/perf_event.h
> @@ -167,6 +167,11 @@ struct x86_pmu_capability {
> #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2)
> #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
>
> +/* TOPDOWN.SLOTS: */
> +#define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
> +#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3)
> +#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
> +
> /*
> * We model BTS tracing as another fixed-mode PMC.
> *


This whole second hunk does not belong in this patch, probably the next
one.

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