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SubjectRe: [PATCH v3 4/4] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver
Date
Hello,

Martin Blumenstingl wrote:
> The mainline PCIe PHY driver has it's own devicetree node. Update the
> clock alias so the mainline driver finds the clocks.
>
> The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
> and GRX390.
> The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
> GRX390.
> The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
> Lantiq's board support package (called "UGW") names these registers
> "PDI".

Applied to mips-next.

> commit ed90302be64a
> https://git.kernel.org/mips/c/ed90302be64a
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Signed-off-by: Paul Burton <paul.burton@mips.com>

Thanks,
Paul

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