[lkml]   [2019]   [Aug]   [24]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v3 4/4] MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driver

Martin Blumenstingl wrote:
> The mainline PCIe PHY driver has it's own devicetree node. Update the
> clock alias so the mainline driver finds the clocks.
> The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
> and GRX390.
> The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
> GRX390.
> The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
> Lantiq's board support package (called "UGW") names these registers
> "PDI".

Applied to mips-next.

> commit ed90302be64a
> Signed-off-by: Martin Blumenstingl <>
> Signed-off-by: Paul Burton <>


[ This message was auto-generated; if you believe anything is incorrect
then please email to report it. ]

 \ /
  Last update: 2019-08-24 16:14    [W:0.068 / U:2.060 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site