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SubjectRe: [PATCH v3 0/8] AMD64 EDAC fixes
On Thu, Aug 22, 2019 at 10:35:48AM +0200, Borislav Petkov wrote:
> On Thu, Aug 22, 2019 at 02:50:20AM +0200, Adam Borowski wrote:
> > While you're editing that code, could you please also cut the spam if ECC is
> > actually disabled? For example, a 2990WX with non-ECC RAM gets 1024 lines;
>
> Patch is in there. I'll give you extra points if you spot it.

Yeah, some of messages are no longer emitted for memory-less nodes (NUMA 1
and 3). Your patch set also overhauls the messages.

But, the amount of redundant messages I'm complaining about has actually
increased:

dmesg|grep EDAC|cut -c 16-|sort|uniq -c
256 EDAC MC: UMC0 chip selects:
256 EDAC MC: UMC1 chip selects:
1 EDAC MC: Ver: 3.0.0
128 EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load.
^ three lines each
64 EDAC amd64: F17h detected (node 0).
64 EDAC amd64: F17h detected (node 1).
64 EDAC amd64: F17h detected (node 2).
64 EDAC amd64: F17h detected (node 3).
512 EDAC amd64: MC: 0: 0MB 1: 0MB
256 EDAC amd64: MC: 2: 0MB 3: 0MB
256 EDAC amd64: MC: 2: 8192MB 3: 0MB
64 EDAC amd64: Node 0: DRAM ECC disabled.
64 EDAC amd64: Node 2: DRAM ECC disabled.
256 EDAC amd64: using x4 syndromes.

(Full dmesg at http://ix.io/1T1o)

While on 5.3-rc5 without the patchset I get:

1 EDAC MC: Ver: 3.0.0
256 EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load.
^ three lines each
64 EDAC amd64: Node 0: DRAM ECC disabled.
64 EDAC amd64: Node 1: DRAM ECC disabled.
64 EDAC amd64: Node 2: DRAM ECC disabled.
64 EDAC amd64: Node 3: DRAM ECC disabled.

So I wonder if we could deduplicate those.


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