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SubjectRe: [PATCH] dma-mapping: fix page attributes for dma_mmap_*
On Fri, Aug 02, 2019 at 10:14:41AM +0200, Christoph Hellwig wrote:
> On Thu, Aug 01, 2019 at 05:44:12PM +0100, Will Deacon wrote:
> > > > Although arch_dma_mmap_pgprot() is a bit of a misnomer now that it only
> > > > gets involved in the non-coherent case.
> > >
> > > A better name is welcome.
> >
> > How about arch_dma_noncoherent_mmap_pgprot() ? Too long?
>
> Sounds a little long yes. And doesn't fix the additional problem that
> we don't just it for mmap but also for the in-kernel remapping these
> days.

Hmm. Maybe just arch_dma_noncoherent_pgprot() then.

> > > But my worry is how this interacts with architectures that have an
> > > uncached segment (mips, nios2, microblaze, extensa) where we'd have
> > > the kernel access DMA_ATTR_WRITE_COMBINE mappigns using the uncached
> > > segment, and userspace mmaps using pgprot_writecombine, which could
> > > lead to aliasing issues. But then again mips already supports
> > > DMA_ATTR_WRITE_COMBINE, so this must be ok somehow. I guess I'll
> > > need to field that question to the relevant parties.
> >
> > Or it's always been busted and happens to work out in practice...
>
> I've sent a ping to the mips folks. While we'are at it: arm64
> and arm32 (optionally) map dma coherent allocations as write combine.
> I suspect this hasn't always just been busted but intentional (of course!),
> but is there any chance to get a quote from the arm architecture spec
> on why this is fine as it looks rather confusion?

So this boils down to a terminology mismatch. The Arm architecture doesn't have
anything called "write combine", so in Linux we instead provide what the Arm
architecture calls "Normal non-cacheable" memory for pgprot_writecombine().
Amongst other things, this memory type permits speculation, unaligned accesses
and merging of writes. I found something in the architecture spec about
non-cachable memory, but it's written in Armglish[1].

pgprot_noncached(), on the other hand, provides what the architecture calls
Strongly Ordered or Device-nGnRnE memory. This is intended for mapping MMIO
(i.e. PCI config space) and therefore forbids speculation, preserves access
size, requires strict alignment and also forces write responses to come from
the endpoint.

I think the naming mismatch is historical, but on arm64 we wanted to use the
same names as arm32 so that any drivers using these things directly would get
the same behaviour.

Will

[1]

B2.4.4 Implication of caches for the application programmer

[...]

Data coherency issues

Software can ensure the data coherency of caches in the following ways:

* By not using the caches in situations where coherency issues can arise.
This can be achieved by:

- Using Non-cacheable or, in some cases, Write-Through Cacheable memory.

- Not enabling caches in the system.

* By using cache maintenance instructions to manage the coherency issues
in software.

* By using hardware coherency mechanisms to ensure the coherency of data
accesses to memory for cacheable locations by observers within the
different shareability domains.

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