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SubjectRe: [PATCH] riscv: move sifive_l2_cache.c to drivers/soc
On Mon, Aug 19, 2019 at 08:09:04AM +0200, Borislav Petkov wrote:
> On Sun, Aug 18, 2019 at 10:29:35AM +0200, Christoph Hellwig wrote:
> > The sifive_l2_cache.c is in no way related to RISC-V architecture
> > memory management. It is a little stub driver working around the fact
> > that the EDAC maintainers prefer their drivers to be structured in a
> > certain way
> That changed recently so I guess we can do the per-IP block driver after
> all, if people would still prefer it.

That would seem like the best idea. But I don't really know this code
well enough myself, and I really need to get this code out of the
forced on RISC-V codebase as some SOCs I'm working with simply don't
have the memory for it..

So unless someone signs up to do a per-IP block edac drivers instead
very quickly I'd still like to see something like this go into 5.4
for now.

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