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SubjectRe: [PATCHv5 1/2] dt-bindings: coresight: Change CPU phandle to required property
Hi Greg,

On Thu, 27 Jun 2019 at 12:15, Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> Do not assume the affinity to CPU0 if cpu phandle is omitted.
> Update the DT binding rules to reflect the same by changing it
> to a required property.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

I'm all good with this patch - can you pick this up for the coming
merge window? If not I'll simply keep it in my tree for 5.4.

Tested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> ---
> .../devicetree/bindings/arm/coresight-cpu-debug.txt | 4 ++--
> Documentation/devicetree/bindings/arm/coresight.txt | 8 +++++---
> 2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> index 298291211ea4..f1de3247c1b7 100644
> --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> @@ -26,8 +26,8 @@ Required properties:
> processor core is clocked by the internal CPU clock, so it
> is enabled with CPU clock by default.
>
> -- cpu : the CPU phandle the debug module is affined to. When omitted
> - the module is considered to belong to CPU0.
> +- cpu : the CPU phandle the debug module is affined to. Do not assume it
> + to default to CPU0 if omitted.
>
> Optional properties:
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 8a88ddebc1a2..fcc3bacfd8bc 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -59,6 +59,11 @@ its hardware characteristcs.
>
> * port or ports: see "Graph bindings for Coresight" below.
>
> +* Additional required property for Embedded Trace Macrocell (version 3.x and
> + version 4.x):
> + * cpu: the cpu phandle this ETM/PTM is affined to. Do not
> + assume it to default to CPU0 if omitted.
> +
> * Additional required properties for System Trace Macrocells (STM):
> * reg: along with the physical base address and length of the register
> set as described above, another entry is required to describe the
> @@ -87,9 +92,6 @@ its hardware characteristcs.
> * arm,cp14: must be present if the system accesses ETM/PTM management
> registers via co-processor 14.
>
> - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
> - source is considered to belong to CPU0.
> -
> * Optional property for TMC:
>
> * arm,buffer-size: size of contiguous buffer space for TMC ETR
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>

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