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Subject[PATCH v5 0/6] Support for Allwinner V3/S3L and Sochip S3
This patchset tries to add support for Allwinner V3/S3L and Sochip S3.

Allwinner V3/V3s/S3L and Sochip S3 share the same die, but with
different package. V3 is BGA w/o co-packaged DDR, V3s is QFP w/ DDR2,
S3L is BGA w/ DDR2 and S3 is BGA w/ DDR3. (S3 and S3L is compatible
for pinout, but because of different DDR, DDR voltage is different
between the two variants). Because of the pin count of V3s is
restricted due to the package, some pins are not bound on V3s, but
they're bound on V3/S3/S3L.

Currently the kernel is only prepared for the features available on V3s.
This patchset adds the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.

Icenowy Zheng (6):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
clk: sunxi-ng: v3s: add Allwinner V3 support
ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs
dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board
ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3

.../devicetree/bindings/arm/sunxi.yaml | 6 +
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts | 53 ++++
arch/arm/boot/dts/sun8i-v3.dtsi | 14 +
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 231 ++++++++++++++-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265 +++++++++++++++++-
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 +
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
10 files changed, 573 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi


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