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SubjectRe: [PATCH] KVM: arm64: Update kvm_arm_exception_class and esr_class_str for new EC
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Hi,

I noticed Marc had applied this patch in his kvmarm tree, with the
updated commit message. Thanks Marc :)

On 2019/7/25 20:48, James Morse wrote:
> Hi,
>
> On 13/07/2019 05:40, Zenghui Yu wrote:
>> We've added two ESR exception classes for new ARM hardware extensions:
>> ESR_ELx_EC_PAC and ESR_ELx_EC_SVE.
>>
>> This patch updates "kvm_arm_exception_class" for these two EC, which the
>
>> new EC will be parsed in kvm_exit trace events (for guest's usage of
>
> new EC will be visible to user-space via kvm_exit() trace events... ?
>
>
>> Pointer Authentication and Scalable Vector Extension). The same updates
>> to "esr_class_str" for ESR_ELx_EC_PAC, by which we can get more accurate
>> debug info.
>
> Its accurate either way round. This stops the trace-point print from printing the EC in
> hex, instead giving it a name, like we do for all the others.

So this should be "readable".

>> Trivial changes, update them in one go.
>
> (I don't think this bit needs to go in the git-log!)
>
>
>> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
>> index a8b205e..ddf9d76 100644
>> --- a/arch/arm64/include/asm/kvm_arm.h
>> +++ b/arch/arm64/include/asm/kvm_arm.h
>> @@ -316,9 +316,10 @@
>>
>> #define kvm_arm_exception_class \
>> ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
>> - ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
>> - ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
>> - ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
>> + ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
>> + ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
>> + ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
>> + ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
>> ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
>> ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
>> ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
>
> Do we need to add:
> ESR_ELx_EC_ILL
> ESR_ELx_EC_HVC32
> ESR_ELx_EC_SMC32

I think they're needed. But these three EC are not included into
kvm_arm_exception_class at the time it was introduced, I don't know
the reason.

> (I don't see how any of the _CUR entries could ever happen as these EC originally come
> from ESR_EL2, but they're harmless)

(I agree with you.)

>> diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
>> index 8c03456..969e156 100644
>> --- a/arch/arm64/kernel/traps.c
>> +++ b/arch/arm64/kernel/traps.c
>> @@ -734,6 +734,7 @@ asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)
>> [ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC",
>> [ESR_ELx_EC_FP_ASIMD] = "ASIMD",
>> [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS",
>> + [ESR_ELx_EC_PAC] = "PAC",
>> [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC",
>> [ESR_ELx_EC_ILL] = "PSTATE.IL",
>> [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
>
>
> Reviewed-by: James Morse <james.morse@arm.com>

Thanks for your reviewing!


Zenghui


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