| Date | Tue, 2 Jul 2019 22:02:00 -0400 | From | Sasha Levin <> | Subject | Re: [PATCH 5.1 51/55] bpf, arm64: use more scalable stadd over ldxr / stxr loop in xadd |
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On Tue, Jul 02, 2019 at 10:01:59AM +0200, Greg Kroah-Hartman wrote: >From: Daniel Borkmann <daniel@iogearbox.net> > >commit 34b8ab091f9ef57a2bb3c8c8359a0a03a8abf2f9 upstream. > >Since ARMv8.1 supplement introduced LSE atomic instructions back in 2016, >lets add support for STADD and use that in favor of LDXR / STXR loop for >the XADD mapping if available. STADD is encoded as an alias for LDADD with >XZR as the destination register, therefore add LDADD to the instruction >encoder along with STADD as special case and use it in the JIT for CPUs >that advertise LSE atomics in CPUID register. If immediate offset in the >BPF XADD insn is 0, then use dst register directly instead of temporary >one. > >Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> >Acked-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> >Acked-by: Will Deacon <will.deacon@arm.com> >Signed-off-by: Alexei Starovoitov <ast@kernel.org> >Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This one has a fix upstream: c5e2edeb01ae9ffbdde95bdcdb6d3614ba1eb195 ("arm64: insn: Fix ldadd instruction encoding").
-- Thanks, Sasha
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