| From | Krzysztof Kozlowski <> | Date | Wed, 17 Jul 2019 12:35:01 +0200 | Subject | Re: [PATCH v1 33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420 |
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On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote: > > Change the parents of UART clocks to the CPLL which has 666MHz. > The UARTs' dividers use /10 rate so they would have 66.6MHz.
Write also the state before to show what is being fixed (I assume previous frequency was not best choice).
BR, Krzysztof
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